陳衍昊 (Chen, Yen-Hao)

Hello, I am Yen-Hao Chen, a Ph.D. student at National Tsing Hua University, Taiwan.
 
I received my B.S. degree in Computer Science and Engineering from Yuan Ze University, Taoyuan, Taiwan, in 2012. I obtained an M.S. degree in Computer Science from National Tsing Hua University, Hsinchu, Taiwan, in 2014. I am currently a Ph. D. student in the Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan. My research interests include physical design automation and computer architecture.

 

Publications

  1. Yen-Hao Chen, Allen C.-H. Wu, and TingTing Hwang, "A Dynamic Link-latency Aware Cache Replacement Policy (DLRP)," in Proceedings of the 26th Asia and South Pacific Design Automation Conference (ASPDAC), pp. 210-215, January 2021.
    [paper] [slide] [video]
  2. Yen-Hao Chen, Po-Chen Huang, Fu-Wei Chen, Allen C.-H. Wu, and TingTing Hwang, "Crosstalk-aware TSV-buffer Insertion in 3D IC," in Proceedings of IEEE International System-on-Chip Conference (SOCC), Singapore, pp. 400-405, September 2019. (Best paper award)
    [ paper ] [s lide]
  3. Pei-An Ho, Yen-Hao Chen, Allen C.-H. Wu, and TingTing Hwang, "Timing Aware Wrapper Cells Reduction for Pre-bond Testing in 3D-ICs," in Proceedings of IEEE International System-on-Chip Conference (SOCC), Singapore, pp. 236-241, September 2019.
    [ paper ] [poster]
  4. Yen-Hao Chen, Allen C. Wu, TingTing Hwang, "Interference-Aware Cache Replacement Policy in MPSoC," in Proceedings of Design Automation Conference (DAC), June 2018. (WIP)
  5. Yen-Hao Chen, Yi-Lun Tang, Yi-Yu Liu, Allen C. H. Wu, TingTing Hwang, "A Novel Cache-Utilization Based Dynamic Voltage Frequency Scaling (DVFS) Mechanism for Reliability Enhancements," in Proceedings of IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), vol. 25, Iss. 3, pp. 820-832, March 2017.
    [paper]
  6. YenHao Chen, Chien-Pang Chiu, Russell Barnes and TingTing Hwang, "Architectural Evaluations on TSV Redundancy for Reliability Enhancement," in Proceedings of ACM/IEEE Design, Automation and Testing in Europe (DATE), pp. 566-571, March 2017.
    [paper] [slide]
  7. Chia-Ling Chen, Yen-Hao Chen, TingTing Hwang, "Communication Driven Remapping of Processing Element (PE) in Fault-tolerant NoC-based MPSoCs," in Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 666-671, January 2017.
    [paper] [slide]
  8. Yen-Hao Chen, Yi-Lun Tang, Yi-Yu Liu, Allen C. H. Wu, TingTing Hwang, "A Novel Cache-Utilization Based Dynamic Voltage Frequency Scaling (DVFS) Mechanism for Reliability Enhancements," in Proceedings of Design, Automation and Test in Europe (DATE), pp. 79-84, March 2016.
    [paper] [slide]
  9. Wei Hen Lo, Yen-Hao Chen, TingTing Hwang, "Dynamic Data Migration to Eliminate Bank-Level Interference for Data Parallel Applications in Multicore Systems," in Proceedings of Design Automation Conference (DAC), June 2015. (WIP)
  10. Wei Hen Lo, Yen Hao Chen, TingTing Hwang, "Dynamic Data Migration to Eliminate Bank-level Interference for Stencil Applications in Multicore Systems," in Proceedings of Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 22-27, March 2015.
    [paper] [poster]
  11. Ting-Wei Hung, Yen-Hao Chen, Yi-Yu Liu, "Memory Management for Dual-addressing Memory Architecture," in Proceedings of Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 50-55, October 2013.
    [paper]
  12. Yen-Hao Chen, Yi-Yu Liu, "Dual-addressing memory architecture for two-dimensional memory access patterns," in Proceedings of Design, Automation and Test in Europe (DATE), pp. 71-76, March 2013.
    [paper] [slide]

Projects 研究計畫

 
  1. 先進晶片技術之可靠度設計自動化研究－子計畫二：三維晶片之可靠度技術研究 (Reliability Enhancements in 3D IC Designs), MOST 106-2221-E-007-114-MY3, 2017.08.01~2020.07.31
  2. 適用於【高可靠度多裸晶整合晶片】之【再生性設計方法】之可行性研究-子計畫二：再生多晶片中，考量時間的TSV配置問題 (Timing-Aware TSV Assignment for Regenerative Multi-Die ICs), MOST 104-2220-E007-013, 2015.05.01~2016.04.30
  3. 三維晶片之容錯矽穿通道架構研究 (Fault Tolerant Architecture for TSV in 3D IC), MOST 103-2221-E007-124-MY3, 2014.08.01~2017.07.31
  4. 加寬匯流排多核心平台研究及其於三維圖形計算之應用-子計畫二：加寬匯流排考量下，多核心系統之記憶體層級架構設計 (Wide I/O Driven Memory Hierarchy Design in Many-Core Systems) (3/3), NSC 103-2220-E007-013, 2014.05.01~2015.04.30
    [ report ]
  5. 加寬匯流排多核心平台研究及其於三維圖形計算之應用-子計畫二：加寬匯流排考量下，多核心系統之記憶體層級架構設計 (Wide I/O Driven Memory Hierarchy Design in Many-Core Systems) (2/3), NSC 102-2220-E007-024, 2013.05.01~2014.04.30
  6. 加寬匯流排多核心平台研究及其於三維圖形計算之應用-子計畫二：加寬匯流排考量下，多核心系統之記憶體層級架構設計 (Wide I/O Driven Memory Hierarchy Design in Many-Core Systems) (1/3), NSC 101-2220-E007-024, 2012.05.01~2013.04.30

Honors / Achievements

  1. 科技部108年度補助博士生赴國外研究計畫 (千里馬計畫) - 核定通過 [link]
  2. 一百零六年度聯詠科技獎學金 - 博士班獎學金, 2017. [link1] [link2]
  3. 2017 台灣半導體產業協會(TSIA)半導體獎:博士研究生, 2017. [link1] [link2]
  4. 國立清華大學103學年度校長獎學金, 2014. [link]
  5. 一百零二年度聯詠科技獎學金 - 碩士生獎學金, 2013.
  6. 黃柏晨、陳衍昊, 教育部『100學年度大學校院積體電路電腦輔助設計(CAD)軟體製作競賽』特優 - Finding the Minimal Logic Difference for Functional ECO, 2012.
  7. 100學年度元智大學金質獎章, 2012.
  8. 100學年度元智大學銀質獎章, 2012.
  9. 100學年度元智大學有庠獎學金 (相當於其他大學之書卷獎), 2012
  10. 陳衍昊、許智皓, 教育部『九十九學年度大學校院積體電路電腦輔助設計(CAD)軟體製作競賽』佳作 - Numerical optimization on photo-mask - model-based optical proximity correction, 2011.
  11. 盧天祥、陳衍昊、杜明軒, 2011 ACM NCPU (第一屆全國私立大專院校程式競賽)冠軍, 2011.
  12. 2011 國際大專院校程式設計競賽推廣與培訓 四月份校際例行賽第二名.
  13. 99學年度元智大學有庠獎學金 (相當於其他大學之書卷獎), 2011
  14. 2010元智大學資訊週「c/c++、java程式設計比賽」第二名.
  15. 98學年度元智大學有庠獎學金 (相當於其他大學之書卷獎), 2010
  16. 97學年度元智大學楊明德獎學金, 2009

Stuffs

  1. Polyhedral Representation of Programs, 2014. [slides]
  2. Dynamic Random Access Memory (DRAM) Basic, 2013. [slides]